Altera cyclone V Technical Reference page 260

5-66
l3master
Bit
5:3
smplsel
2:0
drvsel
l3master
Controls the L3 master HPROT AHB-Lite signal. These register bits should be updated only during system
initialization prior to removing the peripheral from reset. They may not be changed dynamically during
peripheral operation All fields are reset by a cold or warm reset.
Module Instance
sysmgr
Offset:
0x10C
Access:
RW
Altera Corporation
Name
Select which phase shift of the clock for cclk_in_
sample. Note that the boot ROM programs this field to
0x0.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Select which phase shift of the clock for cclk_in_drv.
Note that the boot ROM programs this field to 0x3.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
Description
0 degrees phase shifted clock is selected
45 degrees phase shifted clock is selected
90 degrees phase shifted clock is selected
135 degrees phase shifted clock is selected
180 degrees phase shifted clock is selected
225 degrees phase shifted clock is selected
270 degrees phase shifted clock is selected
315 degrees phase shifted clock is selected
Description
Reserved
45 degrees phase shifted clock is selected
90 degrees phase shifted clock is selected
135 degrees phase shifted clock is selected
180 degrees phase shifted clock is selected
225 degrees phase shifted clock is selected
270 degrees phase shifted clock is selected
315 degrees phase shifted clock is selected
Base Address
0xFFD08000
Access
Register Address
0xFFD0810C
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
System Manager
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