Altera cyclone V Technical Reference page 996

14-50
Busy Signal After CE-ATA RW_BLK Write Transfer
1. Issue an SD/SDIO SEND_STATUS (CMD13) command. The controller sends the status of the card as
the response to the command.
2. Check the card's busy status.
3. Wait until the card is not busy.
4. Check the card's transfer status. If the card is in the stand-by state, issue an SD/SDIO SELECT/
DESELECT_CARD (CMD7) command to place it in the transfer state.
Busy Signal After CE-ATA RW_BLK Write Transfer
During CE-ATA RW_BLK write transfers, the MMC busy signal might be asserted after the last block. If
the CE-ATA card device interrupt is disabled (the nIEN bit in the card device's ATA control register is set
to 1), the
dto
cannot issue the CMD60 command to check the ATA busy status after a CMD61 command. Instead, the
host must perform one of the following actions:
• Issue the SEND_STATUS command and check the MMC busy status before issuing a new CMD60
command
• Issue the CMD39 command and check the ATA busy status before issuing a new CMD60 command
For the data transfer commands, software must set the
in the card.
Data Transfer Interrupts
The controller generates an interrupt for different conditions during data transfer, which are reflected in
the following
1.
—Data transfer is over or terminated. If there is a response timeout error, the controller does not
dto
attempt any data transfer and the Data Transfer Over bit is never set.
2. Transmit FIFO data request bit (
software is expected to write data, if available, into the FIFO buffer.
3. Receive FIFO data request bit (
software is expected to read data from the FIFO buffer.
4.
—The FIFO buffer is empty during transmission or is full during reception. Unless software
hto
corrects this condition by writing data for empty condition, or reading data for full condition, the
controller cannot continue with data transfer. The clock to the card is stopped.
5. —The card has not sent data within the timeout period.
bds
6.
—A CRC error occurred during data reception.
dcrc
7.
—The start bit is not received during data reception.
sbe
8.
—The end bit is not received during data reception, or for a write operation. A CRC error is
ebe
indicated by the card.
, , and
dcrc sbe
transfer occurs.
Single-Block or Multiple-Block Read
To implement a single-block or multiple-block read, the software performs the following steps:
1. Write the data size in bytes to the
the block size.
2. Write the block size in bytes to the
in blocks of size
3. If the read round trip delay, including the card delay, is greater than half of
to the card threshold control register (
Altera Corporation
†
†
†
bit in the register is set to 1 even though the card sends MMC BUSY. The host
rintsts
†
†
†
register bits:
rintsts
rxdr
†
indicate that the received data might have errors. If there is a response timeout, no data
ebe
†
†
†
.
blksiz
†
ctype
)​—The FIFO buffer threshold for transmitting data is reached;
txdr
)​—The FIFO buffer threshold for receiving data is reached;
†
†
†
register. For a multi-block read,
bytcnt
register. The controller expects data to return from the card
blksiz
) to ensure that the card clock does not stop in the
cardthrctl
†
register to the bus width that is programmed
†
†
†
†
must be a multiple of
bytcnt
sdmmc_clk_divided
cv_5v4
2016.10.28
†
†
, write
SD/MMC Controller
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