Initializing The Dmac - Altera cyclone V Technical Reference

16-8
Initializing and Clearing of Memory before Enabling ECC
At Barrier
A DMA channel thread is stalled and the DMAC is waiting for transactions on the AXI to complete. After
the AXI transactions complete, the thread returns to the Executing state.
Waiting For Peripheral
A DMA channel thread is stalled and the DMAC is waiting for the peripheral to provide the requested
data. After the peripheral provides the data, the thread returns to the Executing state.
Faulting Completing
A DMA channel thread is waiting for the AXI master interface to signal that the outstanding load or store
transactions are complete. After the transactions complete, the thread moves to the Faulting state.
Faulting
The thread is stalled indefinitely. The thread moves to the Stopped state when you use the
to instruct the DMAC to execute
Killing
A DMA channel thread is waiting for the AXI master interface to signal that the outstanding load or store
transactions are complete. After the transactions complete, the thread moves to the Stopped state.
Completing
A DMA channel thread is waiting for the AXI master interface to signal that the outstanding load or store
transactions are complete. After the transactions complete, the thread moves to the Stopped state.
Related Information
Updating DMA Channel Control Registers During a DMA Cycle
Initializing and Clearing of Memory before Enabling ECC
Due to the DMA controller FIFO implementation, you must initialize and clear the FIFO before you
enable the ECC to avoid a single event upset (SEU).
The following describes the initialization requirements:
• Initialize memory data before enabling ECC
• The ECC syndrome bits can be random if you do not initialize, first.
• The random ECC syndrome bits causes false single- and double-bit errors to occur when reading
the memory.

Initializing the DMAC

The DMAC provides several memory-mapped control signals that initialize its operating state when it
exits from reset. The DMAC does not automatically begin executing code when it exits from reset. The
system manager controls these memory-mapped control signals.
Altera Corporation
for that thread.
DMAKILL
DBGCMD
on page 16-30
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cv_5v4
2016.10.28
register
DMA Controller