Altera cyclone V Technical Reference page 963

cv_5v4
2016.10.28
Internal DMA Controller Interrupts
Interrupts can be generated as a result of various events. The
cause an interrupt. The internal DMA controller interrupt enable register (
for each of the events that can cause an interrupt to occur.
There are two summary interrupts—the normal interrupt summary bit (
summary bit (
( ) and receive interrupt (
ti
error interrupt (
the register.
idsts
Interrupts are cleared by writing a 1 to the corresponding bit position.
position, the write is ignored, and does not clear the interrupt. When all the enabled interrupts within a
group are cleared, the corresponding summary bit is set to 0. When both the summary bits are set to 0, the
interrupt signal is de-asserted.
Interrupts are not queued. If another interrupt event occurs before the driver has responded to the
previous interrupt, no additional interrupts are generated. For example, the
indicates that one or more data has been transferred to the host buffer.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan the
register for the interrupt cause.
interrupts from the BIU and internal DMA controller.
SD/MMC Controller
Send Feedback
)—in the register.
ais idsts
) bits in the
ri
), descriptor unavailable interrupt (
fbe
†
†
The final interrupt signal from the controller is a logical OR of the
Internal DMA Controller Interrupts
idsts
†
†
The bit results from a logical OR of the transmit interrupt
nis
register. The bit is a logical OR result of the fatal bus
idsts ais
), and card error summary interrupt (
du
register contains all the bits that might
) contains an enable bit
idinten
) and the abnormal interrupt
nis
†
If a 0 is written to an interrupt's bit
bit of the
ri idsts
†
Altera Corporation
14-17
) bits in
ces
register
idsts