Altera cyclone V Technical Reference page 573

cv_5v4
2016.10.28
Module Instance
l3regs
Offset:
0x4A100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
read_qos Fields
Bit
3:0
pri
write_qos
QoS (Quality of Service) value for the write channel.
Module Instance
l3regs
Offset:
0x4A104
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Interconnect
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0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
QoS (Quality of Service) value for the read channel. A
higher value has a higher priority.
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
write_qos
Register Address
0xFF84A100
21 20 19 18
5 4 3 2
RW 0x0
Access
Register Address
0xFF84A104
7-125
17 16
1 0
pri
Reset
RW 0x0
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