Using The Slave Interfaces - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
How to Set the Security State of the DMA Manager
The security state of the DMAC manager thread is controlled by a bit in the DMA register in the System
Manager. The
state.
Related Information
DMA Manager Thread in Secure State
•
Describes how the security state of the DMA manager affects how the DMAC operates.
DMA Manager Thread in Non-Secure State
•
How to Set the Security State for the Interrupt Outputs
You can set the security of an event-interrupt resource through the
found in the System Manager register map.
Related Information
Security Usage
Describes how the security state of the irq[x] signals affects how the DMAC executes the DMAWFE and
DMASEV instructions.
How to Set the Security State for a Peripheral Request Interface
You can control the security state of each peripheral request interface by programming bits in the
dma_periph
So if bit 0 is 0, then the peripheral interface 0 operates in the secure state.
Related Information
Security Usage
Describes the effect of the security state of the peripheral request interfaces on the execution of the
DMAWFP, DMALDP, DMASTP, or DMAFLUSHP instructions by a DMA channel thread.

Using the Slave Interfaces

The slave interfaces connect the DMAC to the level 4 (L4) main bus and enable the MPU to access the
registers. Using these registers, the MPU can perform the following functions:
• Access the status of the DMA manager thread
• Access the status of the DMA channel threads
• Enable or clear interrupts
• Enable events
• Execute an instruction for the DMAC by programming the following debug registers:
•
DBGCMD
•
DBGINST0
•
DBGINST1
DMA Controller
Send Feedback
bit controls the security state and when released from reset the DMA is in the secure
mgr_ns
on page 16-26
register found in the System Manager. Each bit corresponds to a peripheral request interface.
on page 16-26
register
register
register
How to Set the Security State of the DMA Manager
on page 16-27
on page 16-27
irq_ns
bitfield in the DMA register
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