Altera cyclone V Technical Reference page 108

cv_5v4
2016.10.28
s2fuser2clk Fields
Bit
20:9
phase
8:0
cnt
en
Contains fields that control the SDRAM Clock Group enables generated from the SDRAM PLL clock
outputs. 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xD8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Clock Manager
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Name
Increment the phase of the VCO output by the value
in this field multiplied by 45 degrees. The
accumulated phase shift is the total shifted amount
since the last assertion of the 'SDRAM All Output
Divider Reset' bit in the SDRAM vco control register.
In order to guarantee the phase shift to a known
value, 'SDRAM clocks output phase align' bit should
be asserted before programming this field. This field is
only writeable by SW when it is zero. HW updates
this field in real time as the phase adjustment is being
made. SW may poll this field waiting for zero
indicating the phase adjustment has completed by
HW.
Divides the VCO frequency by the value+1 in this
field.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Access
Register Address
0xFFD040D8
21 20 19 18
5 4 3 2
s2fus ddrdq
er2cl clk
k
RW
RW 0x1
0x1
2-71
en
Reset
RW 0x0
RW 0x1
17 16
1 0
ddr2x ddrdqscl
dqscl k
k
RW 0x1
RW
0x1
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