Altera cyclone V Technical Reference page 473

Hard processor system
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cv_5v4
2016.10.28
Register
periph_id_1
on page
7-62
periph_id_2
on page
7-62
periph_id_3
on page
7-63
comp_id_0
on page 7-
64
comp_id_1
on page 7-
64
comp_id_2
on page 7-
65
comp_id_3
on page 7-
66
L4 MAIN
Register
fn_mod_bm_iss
7-67
L4 SP
Register
fn_mod_bm_iss
7-68
L4 MP
Register
fn_mod_bm_iss
7-69
System Interconnect
Send Feedback
Offset
Width Acces
0x1FE4
0x1FE8
0x1FEC
0x1FF0
0x1FF4
0x1FF8
0x1FFC
Offset
Width Acces
on page
0x2008
Offset
Width Acces
on page
0x3008
Offset
Width Acces
on page
0x4008
L3 (NIC-301) GPV Registers Address Map
Reset Value
s
32
RO
0xB3
32
RO
0x6B
32
RO
0x0
32
RO
0xD
32
RO
0xF0
32
RO
0x5
32
RO
0xB1
Reset Value
s
32
RW
0x0
Reset Value
s
32
RW
0x0
Reset Value
s
32
RW
0x0
Description
Peripheral ID1 Register
Peripheral ID2 Register
Peripheral ID3 Register
Component ID0 Register
Component ID1 Register
Component ID2 Register
Component ID3 Register
Description
Bus Matrix Issuing Functionality
Modification Register
Description
Bus Matrix Issuing Functionality
Modification Register
Description
Bus Matrix Issuing Functionality
Modification Register
Altera Corporation
7-25

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