Debug Clocks - Altera cyclone V Technical Reference

10-14

Debug Clocks

Debug Clocks
Table 10-5: CoreSight Clocks
ARM Clock Name
ATCLK
(for csCTI)
CTICLK
(for FPGA-
CTICLK
CTI)
(for CTI-0
CTICLK
and CTI-1)
(for csCTM) Clock manager
CTMCLK
(for CTM)
CTMCLK
DAPCLK
PCLKDBG
HCLK
PCLKSYS
SWCLKTCK
Altera Corporation
Clock Source
Clock manager
Clock manager
FPGA fabric
Clock manager
Clock manager
Clock manager
Clock manager
Clock manager
Clock manager
JTAG interface
FPGA fabric
Note: There are two
clock soures.
HPS Clock Signal Name
dbg_at_clk
dbg_at_clk
fpga_cti_clk
mpu_clk
dbg_clk
mpu_clk
dbg_clk
dbg_clk
dbg_clk
l4_mp_clk
dap_tck tpiu_
traceclkin
Note: There are two
signal names.
Description
Trace bus clock.
Cross trigger interface clock for
csCTI. It can be synchronous or
asynchronous to
CTMCLK
Cross trigger interface clock for
FPGA-CTI.
Cross trigger interface clock for
CTI-0 and CTI-1. It can be
synchronous or asynchronous to
.
CTMCLK
Cross trigger matrix clock for
csCTM. It can be synchronous or
asynchronous to
CTICLK
Cross trigger matrix clock for
CTM. It can be synchronous or
asynchronous to
CTICLK
DAP internal clock. It must be
equivalent to .
PCLKDBG
Debug APB (DAPB) clock.
Used by the AHB-Lite master
inside the DAP. It is asynchro‐
nous to . In the HPS, the
DAPCLK
AHB-Lite port uses same clock
as .
DAPCLK
Used by the APB slave port
inside the DAP. It is asynchro‐
nous to .
DAPCLK
The SWJ-DP clock driven by the
external debugger through either
the JTAG interface or the FPGA
fabric. It is asynchronous to
. When through the JTAG
DAPCLK
interface, this clock is the same
as of the JTAG interface.
TCK
CoreSight Debug and Trace
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cv_5v4
2016.10.28
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