Altera cyclone V Technical Reference page 163

4-20
gpo
31 30
15 14
dclkstat Fields
Bit
0
dcntdone
gpo
Provides a low-latency, low-performance, and simple way to drive general-purpose signals to the FPGA
fabric.
Module Instance
fpgamgrregs
Offset:
0x10
Access:
RW
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
This bit is write one to clear. This bit gets set after the
DCLKCNT has counted down to zero (transition
from 1 to 0).
Value
0x0
0x1
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
DCLKCNT is still counting down.
DCLKCNT is done counting down.
Base Address
0xFF706000
Bit Fields
25 24 23 22
value
RW 0x0
9 8 7 6
value
RW 0x0
21 20 19 18
5 4 3 2
Access
Register Address
0xFF706010
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
17 16
1 0
dcntdone
RW 0x0
Reset
RW 0x0
17 16
1 0
FPGA Manager
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