Altera cyclone V Technical Reference page 803

cv_5v4
2016.10.28
31 30
15 14
autopchen
RW 0x0
portcfg Fields
Bit
19:10
autopchen
SDRAM Controller Subsystem
Send Feedback
29 28 27 26
Reserved
13 12 11 10
Name
Auto-Precharge Enable: One bit is assigned to each
control port. For each bit, the encodings are as
follows:
Value
0x0
0x1
The bits in this field correspond to the control
ports as follows:
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Fields
25 24 23 22
9 8 7 6
Description
Description
The controller requests an automatic
precharge following a bus command
completion (close the row automatically)
The controller attempts to keep a row
open. All active ports with random
dominated operations should set the
bit to 1.
autopchen
CPU write
L3 write
CPU read
L3 read
FPGA-to-SDRAM port 5
FPGA-to-SDRAM port 4
FPGA-to-SDRAM port 3
FPGA-to-SDRAM port 2
FPGA-to-SDRAM port 1
FPGA-to-SDRAM port 0
portcfg
21 20 19 18
autopchen
RW 0x0
5 4 3 2
portprotocol
Access
RW
11-65
17 16
1 0
Reset
0x0
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