Altera cyclone V Technical Reference page 123

3-12
Reset Sequencing
Figure 3-3: Cold Reset Timing Diagram
(2)
nPOR pin (1)
clk_mgr_cold_rst_n
l3_rst_n
miscmod_rst_n
dbg_rst_n
mpu_clkoff[0]
mpu_rst_n[0]
mpu_wd_rst_n
mpu_scu_rst_n
mpu_periph_rst_n
mpu_l2_rst_n
peripheral resets
(1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins.
(2) This dependency applies to all the reset signals.
Altera Corporation
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cv_5v4
2016.10.28
Software
brings out
of reset
32 32
Reset Manager
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