Quad Spi Flash Controller Block Diagram And System Integration - Altera cyclone V Technical Reference

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Quad SPI Flash Controller Block Diagram and System Integration

Quad SPI Flash Controller Block Diagram and System Integration
Figure 15-1: Quad SPI Flash Controller Block Diagram and System Integration
DMA
Controller
System
Manager
L3
Interconnect
The quad SPI controller consists of the following blocks and interfaces:
• Register slave interface—Slave interface that provides access to the control and status registers (CSRs)
• Data slave controller—Slave interface and controller that provides the following functionality:
• Performs data transfers to and from the level 3 (L3) interconnect
• Validates incoming accesses
• Performs byte or half-word reordering
• Performs write protection
• Forwards transfer requests to direct and indirect controller
• Direct access controller—provides memory-mapped slaves direct access to the flash memory
• Indirect access controller—provides higher-performance access to the flash memory through local
buffering and software transfer requests
Altera Corporation
Quad SPI Flash Controller
DMA
Peripheral DMA Peripheral
Request Controller
Request
Interface
ECC
Signals
SRAM
Data Slave Data Slave
Interface Controller
Indirect
Access
Controller
Direct
Access Command
Controller Generator
STIG
CSRs
Register Slave Interface
L4 Peripheral Bus
SPI PHY
TX
FIFO
Flash
RX
FIFO
SPI
Control
Logic
Quad SPI Flash Controller
cv_5v4
2016.10.28
SPI Flash
Device
Interface
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