Altera cyclone V Technical Reference page 341

cv_5v4
2016.10.28
MIXED1IO15 Fields
Bit
1:0
sel
MIXED1IO16
This register is used to control the peripherals connected to qspi_io1 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x540
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MIXED1IO16 Fields
Bit
1:0
sel
System Manager
Send Feedback
Name
Select peripheral signals connected qspi_io0. 0 : Pin is
connected to GPIO/LoanIO number 29. 1 : Pin is
connected to Peripheral signal USB1.CLK. 2 : Pin is
connected to Peripheral signal not applicable. 3 : Pin
is connected to Peripheral signal QSPI.IO0.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected qspi_io1. 0 : Pin is
connected to GPIO/LoanIO number 30. 1 : Pin is
connected to Peripheral signal USB1.STP. 2 : Pin is
connected to Peripheral signal not applicable. 3 : Pin
is connected to Peripheral signal QSPI.IO1.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
MIXED1IO16
Access
Register Address
0xFFD08540
21 20 19 18
5 4 3 2
Access
5-147
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
Altera Corporation