Altera cyclone V Technical Reference page 228

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

5-34
indiv
Bit
3
bscanintf
2
configiointf
1
jtagenintf
Altera Corporation
Name
Used to disable the boundary-scan interface. This
interface allows the FPGA JTAG TAP controller to
execute boundary-scan instructions such as
SAMPLE/PRELOAD, EXTEST, and HIGHZ. The
boundary-scan interface must be enabled before
attempting to send the boundary-scan instructions to
the FPGA JTAG TAP controller.
Value
0x0
0x1
Used to disable the CONFIG_IO interface. This
interface allows the FPGA JTAG TAP controller to
execute the CONFIG_IO instruction and configure all
device I/Os (FPGA and HPS). This is typically done
before executing boundary-scan instructions. The
CONFIG_IO interface must be enabled before
attempting to send the CONFIG_IO instruction to
the FPGA JTAG TAP controller.
Value
0x0
0x1
Used to disable the JTAG enable interface. This
interface allows logic in the FPGA fabric to disable
the HPS JTAG operation.
Value
0x0
0x1
Description
Description
Boundary-scan interface is disabled.
Execution of boundary-scan instructions in
the FPGA JTAG TAP controller is
unsupported and produces undefined results.
Boundary-scan interface is enabled.
Execution of the boundary-scan instructions
in the FPGA JTAG TAP controller is
supported.
Description
CONFIG_IO interface is disabled. Execution
of the CONFIG_IO instruction in the FPGA
JTAG TAP controller is unsupported and
produces undefined results.
CONFIG_IO interface is enabled. Execution
of the CONFIG_IO instruction in the FPGA
JTAG TAP controller is supported.
Description
JTAG enable interface is disabled. Logic in
the FPGA fabric cannot disable the HPS
JTAG.
JTAG enable interface is enabled. Logic in the
FPGA fabric can disable the HPS JTAG.
cv_5v4
2016.10.28
Access
Reset
RW
0x1
RW
0x1
RW
0x1
System Manager
Send Feedback

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents