Altera cyclone V Technical Reference page 29

Hard processor system
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cv_5v4
2016.10.28
Related Information
USB 2.0 OTG Controller
Universal Serial Bus (USB) website
Additional information is available in the On The Go and Embedded Host Supplement to the USB
Revision 2.0 Specification, which you can download from the USB Implementers Forum website.
2
I
C Controllers
2
The four I
features:
• Two controllers support I
• Support both 100 KBps and 400 KBps modes
• Support both 7-bit and 10-bit addressing modes
• Support master and slave operating mode
• Direct access for host processor
• DMA controller may be used for large transfers
Related Information
I2C Controller
UARTs
The HPS provides two UART controllers to provide asynchronous serial communications. The two UART
modules are based on Synopsys DesignWare APB Universal Asynchronous Receiver/ Transmitter
peripheral and offer the following features:
• 16550-compatible UART
• Support automatic flow control as specified in 16750 standard
• Programmable baud rate up to 6.25 MBaud (with 100MHz reference clock)
• Direct access for host processor
• DMA controller may be used for large transfers
• 128-byte transmit and receive FIFO buffers
Related Information
UART Controller
CAN Controllers
The two CAN controllers are based on the Bosch
• Compliant with CAN protocol specification 2.0 part A & B
• Programmable communication rate up to 1 Mbps
• Holds up to 128 messages
• Supports 11-bit standard and 29-bit extended identifiers
• Programmable interrupt scheme
• Direct access for host processor
• DMA controller may be used for large transfers
Related Information
CAN Controller
Introduction to the Hard Processor System
Send Feedback
on page 18-1
C controllers are based on Synopsys DesignWare APB I
2
C management interfaces for use by the EMAC controllers
on page 20-1
on page 21-1
on page 25-1
2
C controller which offer the following
D_CAN controller and offer the following features:
®
1-13
2
I
C Controllers
Altera Corporation

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