Error Detection - Altera cyclone V Technical Reference

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Error Detection

• Clock can be disabled by writing to the
• When low-power mode is selected and the card is idle for at least eight clock cycles.
• FIFO buffer is full, data path cannot accept more data from the card, and data transfer is incomplete—
to avoid FIFO buffer overflow.
• FIFO buffer is empty, data path cannot transmit more data to the card, and data transfer is incomplete
—to avoid FIFO buffer underflow.
Note: The card clock must be disabled through the
values of the
Error Detection
Errors can occur during card operations within the CIU in the following situations.
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Response
• Response timeout—did not receive the response expected with response start bit within the specified
number of clock cycles in the timeout register.
• Response CRC error—response is expected and check response CRC requested; response CRC-7 does
not match with the internally-generated CRC-7.
• Response error—response transmission bit is not 0, command index does not match with the
command index of the send command, or response end bit is not 1.
Data Transmit
• No CRC status—during a write data transfer, if the CRC status start bit is not received for two clock
cycles after the end bit of the data block is sent out, the data path performs the following actions:
• Signals no CRC status error to the BIU
• Terminates further data transfer
• Signals data transfer done to the BIU
• Negative CRC—if the CRC status received after the write data block is negative (that is, not 0b010), the
data path signals a data CRC error to the BIU and continues with the data transfer.
• Data starvation due to empty FIFO buffer—if the FIFO buffer becomes empty during a write data
transmission, or if the card clock stopped and the FIFO buffer remains empty for a data-timeout
number of clock cycles, the data path signals a data-starvation error to the BIU and the data path
continues to wait for data in the FIFO buffer.
Altera Corporation
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and
clkdiv clksrc
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register.
clkena
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register before the host software changes the
clkena
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registers.
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SD/MMC Controller
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cv_5v4
2016.10.28
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