Altera cyclone V Technical Reference page 258

5-64
SDMMC Controller Group Register Descriptions
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ctrl Fields
Bit
1
ensfmdwru
0
waitstate
SDMMC Controller Group Register Descriptions
Registers related to SDMMC Controller which aren't located inside the SDMMC itself.
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Controls whether the wait state bit is updated upon
deassertion of warm reset. This field is set on a cold
reset.
Value
0x0
0x1
Controls the number of wait states applied to the Boot
ROM's read operation. This field is cleared on a cold
reset and optionally updated by hardware upon
deassertion of warm reset.
Value
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Wait state bit is not updated upon deassertion
of warm reset.
Wait state bit is updated upon deassertion of
warm reset. It's value is updated based on the
control bit from clock manager which
specifies whether clock manager will be in
safe mode or not after warm reset.
Description
No wait states are applied to the Boom
ROM's read operation.
A single wait state is applied to the Boot
ROM's read operation.
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
17 16
1 0
ensfm waitstat
dwru e
RW RW 0x0
0x1
Reset
RW 0x1
RW 0x0
System Manager
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