Altera cyclone V Technical Reference page 66

cv_5v4
2016.10.28
inter
Contains fields that indicate the PLL lock status. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
inter Fields
Bit
8
sdrplllocked
7
perplllocked
6
mainplllocked
5
sdrplllost
4
perplllost
Clock Manager
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0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
If 1, the SDRAM PLL is currently locked. If 0, the
SDRAM PLL is currently not locked.
If 1, the Peripheral PLL is currently locked. If 0, the
Peripheral PLL is currently not locked.
If 1, the Main PLL is currently locked. If 0, the Main
PLL is currently not locked.
If 1, the SDRAM PLL has lost lock at least once since
this bit was cleared. If 0, the SDRAM PLL has not lost
lock since this bit was cleared.
If 1, the Peripheral PLL has lost lock at least once
since this bit was cleared. If 0, the Peripheral PLL has
not lost lock since this bit was cleared.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
sdrpl perpl mainp
llock llock llloc
ed ed ked
RO RO RO
0x0 0x0 0x0
Description
Register Address
0xFFD04008
21 20 19 18
5 4 3 2
sdrpl perpl mainp sdrpl
llost llost lllos lachi
t eved
RW RW
0x0 0x0 RW RW
0x0 0x0
Access
2-29
inter
17 16
1 0
perpl mainplla
lachi chieved
eved
RW 0x0
RW
0x0
Reset
RO 0x0
RO 0x0
RO 0x0
RW 0x0
RW 0x0
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