Altera cyclone V Technical Reference page 81

2-44
dbgdiv
Bit
3:2
l3spclk
1:0
l3mpclk
dbgdiv
Contains fields that control clock dividers for debug clocks derived from the Main PLL Fields are only
reset by a cold reset.
Module Instance
clkmgr
Offset:
0x68
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
The l3_sp_clk is divided down from the l3_mp_clk by
the value specified in this field.
0x0
0x1
The l3_mp_clk is divided down from the l3_main_clk
by the value specified in this field.
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Value
Divide by 1
Divide by 2
Value
Divide by 1
Divide by 2
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Description
Register Address
0xFFD04068
21 20 19 18
5 4 3
dbgclk
RW 0x1
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
17 16
2 1 0
dbgatclk
RW 0x0
Clock Manager
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