Altera cyclone V Technical Reference page 492

Hard processor system
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7-44
l4osc1
31
30
15
14
l4osc1 Fields
Bit
6
osc1timer1
5
osc1timer0
4
sysmgr
Altera Corporation
29
28
27
26
13
12
11
10
Reserved
Name
Controls whether secure or non-secure masters can
access the OSC1 Timer 1 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the OSC1 Timer 0 slave.
Value
0x0
0x1
Controls whether secure or non-secure masters can
access the System Manager slave.
Value
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
osc1t
imer1
WO
0x0
Description
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
Description
The slave can only be accessed by a secure
master.
The slave can only be accessed by a secure or
non-secure masters.
21
20
19
18
5
4
3
2
osc1t
sysmg
rstmg
clkmg
imer0
r
r
r
WO
WO
WO
WO
0x0
0x0
0x0
0x0
cv_5v4
2016.10.28
17
16
1
0
l4wd1
l4wd0
WO
WO 0x0
0x0
Access
Reset
WO
0x0
WO
0x0
WO
0x0
System Interconnect
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