Trace Funnel - Altera cyclone V Technical Reference

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

cv_5v4
2016.10.28
ARM Infocenter
For more information, refer to the CoreSight System Trace Macrocell Technical Reference Manual on the
ARM Infocenter website.
csCTI
on page 10-19

Trace Funnel

The Trace Funnel is used to combine multiple trace streams into one trace stream. There are three trace
streams that use the following funnel ports:
Table 10-1: Trace Stream Connections
Funnel Port
0
1
2
3
4 .. 7
Related Information
ARM Infocenter
Refer to the CoreSight Components Technical Reference Manual on the ARM Infocenter website.
Program Trace Macrocell
CoreSight Trace Memory Controller
The CoreSight Trace Memory Controller (TMC) has three possible configurations:
• Embedded Trace FIFO (ETF)
• Embedded Trace Router (ETR)
• Embedded Trace Buffer (ETB)
ETB is not used in this device.
Related Information
ARM Infocenter
For more information, refer to the CoreSight System Trace Memory Controller Technical Reference Manual
on the ARM Infocenter website.
Embedded Trace FIFO
The Trace Funnel output is sent to the ETF. The ETF is used as an elastic buffer between trace generators
(STM, PTM) and trace destinations. The ETF stores up to 32 KB of trace data in the on-chip trace RAM.
CoreSight Debug and Trace
Send Feedback
The trace stream coming from PTM connected to CPU0 uses this port.
The trace stream coming from PTM connected to CPU1 uses this port.
Not connected.
The trace stream coming from STM uses this port.
Not connected.
on page 10-11
Description
10-5
Trace Funnel
Altera Corporation

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents