Altera cyclone V Technical Reference page 229

cv_5v4
2016.10.28
Bit
0
rstreqintf
module
Used to disable signals from the FPGA fabric to individual HPS modules.
Module Instance
sysmgr
Offset:
0x28
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
System Manager
Send Feedback
Name
Used to disable the reset request interface. This
interface allows logic in the FPGA fabric to request
HPS resets. This field disables the following reset
request signals from the FPGA fabric to HPS:[list]
[*]f2h_cold_rst_req_n - Triggers a cold reset of the
HPS[*]f2h_warm_rst_req_n - Triggers a warm reset
of the HPS[*]f2h_dbg_rst_req_n - Triggers a debug
reset of the HPS[/list]
Value
0x0
0x1
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Description
Reset request interface is disabled. Logic in
the FPGA fabric cannot reset the HPS.
Reset request interface is enabled. Logic in
the FPGA fabric can reset the HPS.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
module
Access
Register Address
0xFFD08028
21 20 19 18
5 4 3 2
emac_ emac_
1 0
RW RW
0x0 0x0
5-35
Reset
RW 0x1
17 16
1 0
Reserved
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