Altera cyclone V Technical Reference page 120

cv_5v4
2016.10.28
Module Reset Signal
dbg_rst_n
tap_cold_rst_n
sdram_cold_rst_n
Table 3-8: L3 Group, Generated Module Resets
Module Reset Signal
l3_rst_n
Modules Requiring Software Deassert
The reset manager leaves the reset signal asserted on certain modules even after the rest of the HPS has
come out of reset. These modules are likely to require software configuration before they can safely be
taken out of reset.
When a module that has been held in reset is ready to start running, software can deassert the reset signal
by writing to the appropriate register, shown in the following table.
Table 3-9: Module Reset Signals and Registers
HPS Peripheral
MPU
Ethernet MAC
USB 2.0 OTG
NAND
Quad SPI
Watchdog
Timer
Timer
2
I C
Reset Manager
Send Feedback
Description
Resets debug components
including DAP, trace,
MPU debug logic, and any
user debug logic in the
FPGA fabric
Resets portion of TAP
controller in the DAP that
must be reset on a cold
reset
Resets SDRAM subsystem
(resets logic associated
with cold reset only)
Description
Resets L3 interconnect and
L4 buses
Reset Register
mpumodrst mpu_cpu_rst_n[1]
permodrst emac_rst_n[1:0]
permodrst usb_rst_n[1:0]
permodrst nand_flash_rst_n
permodrst qspi_flash_rst_n
permodrst watchdog_rst_n[1:0]
permodrst osc1_timer_rst_n[1:0]
permodrst sp_timer_rst_n[1:0]
permodrst i2c_rst_n[3:0]
Modules Requiring Software Deassert
Reset Cold Warm
Domai Reset Reset
n
Debug X
TAP X
Syste X X
m
Reset Cold Warm
Domai Reset Reset
n
Syste X X
m
Module Reset Signal
3-9
Debu Software
g Deassert
Reset
X
Debu Software
g Deassert
Reset
Reset Group
MPU
PER
PER
PER
PER
PER
PER
PER
PER
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