Fpga-To-Sdram Protocol Details - Altera cyclone V Technical Reference

11-28

FPGA-to-SDRAM Protocol Details

the FPGA fabric; these bits are set for you when you configure your implementation using the HPS GUI in
Qsys.
The CSRs are configured using a dedicated slave interface, which provides access to the registers. This
region controls all SDRAM operation, MPFE scheduler configuration, and PHY calibration.
The FPGA fabric interface configuration is programmed into the FPGA fabric and the values of these
register bits can be read by software. The ports can be configured without software developers needing to
know how the FPGA-to-HPS SDRAM interface has been configured.
FPGA-to-SDRAM Protocol Details
The following topics summarize signals for the Avalon-MM Bidirectional port, Avalon-MM Write Port,
Avalon-MM Read Port, and AXI port.
Note: If your device has multiple FPGA hardware images, then the same FPGA-to-SDRAM port configu‐
ration should be used across all designs.
Avalon-MM Bidirectional Port
The Avalon-MM bidirectional ports are standard Avalon-MM ports used to dispatch read and write
operations.
Each configured Avalon-MM bidirectional port consists of the signals listed in the following table.
Table 11-15: Avalon-MM Bidirectional Port Signals
Name
clk
read
write
address
readdata
readdatavalid
writedata
byteenable
(29) The Avalon-MM protocol does not allow read and write transactions to be posted concurrently.
Altera Corporation
Bit Width Input/Output
1
1
1
32
32, 64, 128, or 256
1
32, 64, 128, or 256
4, 8, 16, 32
Direction
In Clock for the Avalon-MM interface
In Indicates read transaction
In Indicates write transaction
In Address of the transaction
Out Read data return
Out Indicates the
data in response to a previous read request.
In Write data for a transaction
In Byte enables for each write byte lane
Function
(29)
(29)
signal contains valid
readdata
SDRAM Controller Subsystem
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2016.10.28