Stm Channels - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
ROM Entry
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
A host debugger can access this table at 0x80000000 through the DAP. HPS masters can access this ROM
at 0xFF000000. Registers for a particular CoreSight component are accessed by adding the register offset to
the CoreSight component base address, and adding that total to the base address of the ROM table.
The base address of the ROM table is different when accessed from the debugger (at 0x8000_0000) than
when accessed from any HPS master (at 0xFF000000). For example, the CTI output enable (CTIOUTEN)
register,
CTIOUTEN[2]
value, add the host debugger access address to the ROM table of 0x80000000, to the CTI component base
address of 0x00002000, to the

STM Channels

The STM AXI slave is connected to the MPU, DMA, and FPGA-to-HPS bridge masters. Each master has
up to 65536 channels where each channel occupies 256 bytes of address space, for a total of 16 MB per
master. The HPS address map allocates 48 MB of consecutive address space to the STM AXI slave port,
divided in three 16 MB segments.
Table 10-8: STM AXI Slave Port Address Allocation
Segment
0
1
CoreSight Debug and Trace
Send Feedback
Offset[30:12]
0x00001
0x00002
0x00003
0x00004
0x00005
0x00006
0x00007
0x00100
0x00080
0x00000
at offset 0xA8, can be accessed by the host debugger at 0x800020A8. To derive that
register offset of 0xA8.
CTIOUTEN[2]
Start Address
0xFC000000
0xFD000000
STM Channels
Description
ETF Component Base Address
CTI Component Base Address
TPIU Component Base Address
Trace Funnel Component Base
Address
STM Component Base Address
ETR Component Base Address
FPGA-CTI Component Base
Address
A9 ROM
FPGA ROM
End of ROM
End Address
0xFCFFFFFF
0xFDFFFFFF
Altera Corporation
10-17