Altera cyclone V Technical Reference page 10

TOC-10
EMAC Block Diagram and System Integration.....................................................................................17-4
EMAC Signal Description.........................................................................................................................17-5
EMAC Internal Interfaces.......................................................................................................................17-12
Functional Description of the EMAC................................................................................................... 17-14
Ethernet MAC Programming Model.................................................................................................... 17-63
Ethernet MAC Address Map and Register Definitions.......................................................................17-72
Document Revision History.................................................................................................................17-873
USB 2.0 OTG Controller................................................................................... 18-1
Features of the USB OTG Controller...................................................................................................... 18-2
USB OTG Controller Block Diagram and System Integration............................................................18-4
USB 2.0 ULPI PHY Signal Description...................................................................................................18-5
Functional Description of the USB OTG Controller............................................................................ 18-6
USB OTG Controller Programming Model......................................................................................... 18-13
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Management Interface...................................................................................................................17-3
Acceleration.................................................................................................................................... 17-3
PHY Interface................................................................................................................................. 17-3
HPS EMAC I/O Signals.................................................................................................................17-6
FPGA EMAC I/O Signals..............................................................................................................17-8
PHY Management Interface....................................................................................................... 17-11
DMA Master Interface................................................................................................................ 17-12
Timestamp Interface....................................................................................................................17-12
Transmit and Receive Data FIFO Buffers................................................................................. 17-15
DMA Controller...........................................................................................................................17-16
Descriptor Overview................................................................................................................... 17-29
IEEE 1588-2002 Timestamps..................................................................................................... 17-46
IEEE 1588-2008 Advanced Timestamps...................................................................................17-52
IEEE 802.3az Energy Efficient Ethernet....................................................................................17-55
Checksum Offload....................................................................................................................... 17-56
Frame Filtering............................................................................................................................. 17-56
Clocks and Resets.........................................................................................................................17-61
Interrupts...................................................................................................................................... 17-63
System Level EMAC Configuration Registers..........................................................................17-63
EMAC FPGA Interface Initialization........................................................................................17-65
EMAC HPS Interface Initialization........................................................................................... 17-66
DMA Initialization.......................................................................................................................17-66
EMAC Initialization and Configuration...................................................................................17-67
Performing Normal Receive and Transmit Operation........................................................... 17-68
Stopping and Starting Transmission......................................................................................... 17-68
Programming Guidelines for Energy Efficient Ethernet........................................................ 17-69
Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output.............................. 17-70
EMAC Module Address Map..................................................................................................... 17-72
Supported PHYS.............................................................................................................................18-3
USB OTG Controller Block Description.................................................................................... 18-6
Local Memory Buffer...................................................................................................................18-10
Clocks............................................................................................................................................ 18-10
Resets............................................................................................................................................. 18-10
Interrupts...................................................................................................................................... 18-11