Altera cyclone V Technical Reference page 102

cv_5v4
2016.10.28
Bit
30:25
outreset
24
outresetall
23:22
ssrc
21:16
denom
15:3
numer
Clock Manager
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Name
Resets the individual PLL output counter. For
software to change the PLL output counter without
producing glitches on the respective clock, SW must
set the VCO register respective Output Counter Reset
bit. Software then polls the respective Output Counter
Reset Acknowledge bit in the Output Counter Reset
Ack Status Register. Software then writes the
appropriate counter register, and then clears the
respective VCO register Output Counter Reset bit.
LSB 'outreset[0]' corresponds to PLL output clock C0,
etc. If set to '1', reset output divider, no clock output
from counter. If set to '0', counter is not reset. The
reset value of this bit is applied on a cold reset; warm
reset has no effect on this bit.
Before releasing Bypass, All Output Counter Reset
must be set and cleared by software for correct clock
operation. If '1', Reset phase multiplexer and output
counter state. So that after the assertion all the clocks
output are start from rising edge align. If '0', phase
multiplexer and output counter state not reset and no
change to the phase of the clock outputs.
Controls the VCO input clock source. The PLL must
by bypassed to eosc1_clk before changing this field.
Qsys and user documenation refer to f2s_sdram_ref_
clk as f2h_sdram_ref_clk.
Value
0x0
0x1
0x2
Denominator in VCO output frequency equation. For
incremental frequency change, if the new value lead
to less than 20% of the frequency change, this value
can be changed without resetting the PLL. The
Numerator and Denominator can not be changed at
the same time for incremental frequency changed.
Numerator in VCO output frequency equation. For
incremental frequency change, if the new value lead
to less than 20% of the frequency change, this value
can be changed without resetting the PLL. The
Numerator and Denominator can not be changed at
the same time for incremental frequency changed.
Description
Description
eosc1_clk
eosc2_clk
f2s_sdram_ref_clk
2-65
vco
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x1
RW 0x1
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