Altera cyclone V Technical Reference page 167

4-24
gpio_inten
gpio_int_polarity
Controls the polarity of interrupts that can occur on each GPIO input.
gpio_intstatus
Reports on interrupt status for each GPIO input. The interrupt status includes the effects of masking.
gpio_raw_intstatus
Reports on raw interrupt status for each GPIO input. The raw interrupt status excludes the effects of
masking.
gpio_porta_eoi
This register is written by software to clear edge interrupts generated by each individual GPIO input. This
register always reads back as zero.
gpio_ext_porta
Reading this register reads the values of the GPIO inputs.
gpio_ls_sync
The Synchronization level register is used to synchronize inputs to the l4_mp_clk. All MON interrupts are
already synchronized before the GPIO instance so it is not necessary to setup this register to enable
synchronization.
gpio_ver_id_code
GPIO Component Version
gpio_config_reg2
Specifies the bit width of port A.
gpio_config_reg1
Reports settings of various GPIO configuration parameters
gpio_inten
Allows each bit of Port A to be configured to generate an interrupt or not.
Module Instance
fpgamgrregs
Offset:
0x830
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
on page 4-33
on page 4-36
on page 4-39
on page 4-41
on page 4-44
on page 4-45
on page 4-46
on page 4-47
on page 4-48
0xFF706000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
0xFF706830
2016.10.28
Register Address
FPGA Manager
Send Feedback
cv_5v4