Altera cyclone V Technical Reference page 275

cv_5v4
2016.10.28
emac1 Fields
Bit
8
rxfifoderr
7
rxfifoserr
6
txfifoderr
5
txfifoserr
4
rxfifoinjd
3
rxfifoinjs
2
txfifoinjd
1
txfifoinjs
0
en
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This bit is an interrupt status bit for EMAC1 RXFIFO
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in EMAC1 RXFIFO RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for EMAC1 RXFIFO
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
EMAC1 RXFIFO RAM. Software needs to write 1
into this bit to clear the interrupt status.
This bit is an interrupt status bit for EMAC1 TXFIFO
RAM ECC double bit, non-correctable error. It is set
by hardware when double bit, non-correctable error
occurs in EMAC1 TXFIFO RAM. Software needs to
write 1 into this bit to clear the interrupt status.
This bit is an interrupt status bit for EMAC1 TXFIFO
RAM ECC single, correctable error. It is set by
hardware when single, correctable error occurs in
EMAC1 TXFIFO RAM. Software needs to write 1
into this bit to clear the interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the EMAC1 RXFIFO
RAM. This only injects one double bit error into the
EMAC1 RXFIFO RAM.
Changing this bit from zero to one injects a single,
correctable error into the EMAC1 RXFIFO RAM.
This only injects one error into the EMAC1 RXFIFO
RAM.
Changing this bit from zero to one injects a double,
non-correctable error into the EMAC1 TXFIFO
RAM. This only injects one double bit error into the
EMAC1 TXFIFO RAM.
Changing this bit from zero to one injects a single,
correctable error into the EMAC1 TXFIFO RAM.
This only injects one error into the EMAC1 TXFIFO
RAM.
Enable ECC for EMAC1 RAM
Description
5-81
emac1
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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