Reset Manager - Altera cyclone V Technical Reference

2016.10.28
cv_5v4
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The reset manager generates module reset signals based on reset requests from the various sources in the
HPS and FPGA fabric, and software writing to the module-reset control registers. The reset manager
ensures that a reset request from the FPGA fabric can occur only after the FPGA portion of the system-
on-a-chip (SoC) device is configured.
The HPS contains multiple reset domains. Each reset domain can be reset independently. A reset may be
initiated externally, internally or through software.
Table 3-1: HPS Reset Domains
Domain Name
TAP
Debug
System
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JTAG test access port (TAP) controller, which is used by the debug access port
(DAP).
All debug logic including most of the DAP, CoreSight
to the debug peripheral bus, trace, the microprocessor unit (MPU) subsystem,
and the FPGA fabric.
All HPS logic except what is in the TAP and debug reset domains. Includes non-
debug logic in the FPGA fabric connected to the HPS reset signals.

Reset Manager

Domain Logic
components connected
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