Altera cyclone V Technical Reference page 625

cv_5v4
2016.10.28
Module Instance
lwhps2fpgaregs
Offset:
0x1FFC
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
comp_id_3 Fields
Bit
7:0
preamble
Master Register Group Register Descriptions
Registers associated with master interfaces.
Offset:
0x2000
FPGA2HPS AXI Bridge Registers Register Descriptions
Registers associated with the FPGA2HPS master interface. This master interface provides access to the
registers in the FPGA2HPS AXI Bridge.
Offset:
0x0
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
ahb_cntl
on page 8-44
Sets the block issuing capability to one outstanding transaction.
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
HPS-FPGA Bridges
Send Feedback
0xFF400000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Preamble
on page 8-43
Master Register Group Register Descriptions
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Register Address
0xFF401FFC
21 20 19 18
5 4 3 2
preamble
RO 0xB1
Access
8-43
17 16
1 0
Reset
RO 0xB1
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