Indirect Read Operation With Dma Enabled - Altera cyclone V Technical Reference

15-16

Indirect Read Operation with DMA Enabled

5. Set up the required interrupts through the
6. If the watermark level is used, set the SRAM watermark level through the
7. Start the indirect read operation by setting the
8. Either use the watermark level interrupt or poll the SRAM fill level in the
determine when there is sufficient data in the SRAM.
9. Issue a read transaction to the indirect address to access the SRAM. Repeat
tions are needed to complete the indirect read transfer.
10.Either use the indirect complete interrupt to determine when the indirect read operation has
completed or poll the completion status of the indirect read operation through the indirect completion
status bit (
Related Information
Setting Up the Quad SPI Flash Controller
Indirect Read Operation with DMA Enabled
The following steps describe the general software flow to set up the quad SPI controller for indirect read
operation with the DMA enabled:
1. Perform the steps described in the
2. Set the flash memory start address in the
3. Set the number of bytes to be transferred in the
4. Set the indirect transfer trigger address in the
5. Set the number of bytes for single and burst type DMA transfers in the
6. Optionally set the SRAM watermark level in the
are issued.
7. Start an indirect read access by setting the
8. Either use the indirect complete interrupt to determine when the indirect read operation has
completed or poll the completion status of the indirect read operation through the
ind_ops_done_status
Related Information
Setting Up the Quad SPI Flash Controller
Indirect Write Operation with DMA Disabled
The following steps describe the general software flow to set up the quad SPI controller for indirect write
operation with the DMA disabled:
1. Perform the steps described in the
2. Set the flash memory start address in the
3. Set up the number of bytes to be transferred in the
4. Set the indirect transfer trigger address in the
5. Set up the required interrupts through the interrupt mask register (
6. Optionally set the SRAM watermark level in the
are issued. The value set must be greater than one flash page. For more information, refer to the
Indirect Write Operation
Altera Corporation
) of the
ind_ops_done_status
field of the
on page 15-6 section.
register.
irqmask
field of the
start
register.
indrd
on page 15-15
Setting Up the Quad SPI Flash Controller
register.
indrdstaddr
register.
indrdcnt
indaddrtrig
indrdwater
field of the
start
register.
indrd
on page 15-15
Setting Up the Quad SPI Flash Controller
register.
indwrstaddr
indwrcnt
indaddrtrig
indwrwater
indrdwater
register to 1.
indrd
register to
sramfill
step 8
if more read transac‐
on page 15-15 section.
register.
register.
dmaper
register to control the rate DMA requests
register to 1.
indrd
on page 15-15 section.
register.
register.
).
irqmask
register to control the rate DMA requests
Quad SPI Flash Controller
cv_5v4
2016.10.28
register.
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