Altera cyclone V Technical Reference page 330

5-136
GENERALIO12
GENERALIO12
This register is used to control the peripherals connected to spim0_ss0 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x4B0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GENERALIO12 Fields
Bit
1:0
sel
GENERALIO13
This register is used to control the peripherals connected to uart0_rx Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x4B4
Access:
RW
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected spim0_ss0. 0 : Pin
is connected to GPIO/LoanIO number 60. 1 : Pin is
connected to Peripheral signal UART1.RTS. 2 : Pin is
connected to Peripheral signal CAN1.TX. 3 : Pin is
connected to Peripheral signal SPIM0.SS0.
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD08000
Register Address
0xFFD084B0
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD084B4
cv_5v4
2016.10.28
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
System Manager
Send Feedback