Altera cyclone V Technical Reference page 53

2-16
SDRAM Clock Group
Table 2-10: SDRAM PLL Output Assignments
PLL
SDRAM
The following figure shows clock gating for SDRAM PLL clock group. Clock gate blocks in the diagram
indicate clocks which may be gated off under software control. Software is expected to gate these clocks off
prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.
Figure 2-6: SDRAM Clock Group Divide and Gating
The SDRAM PLL output clocks can be phase shifted in real time in increments of 1/8 the VCO frequency.
Maximum number of phase shift increments is 4096.
Table 2-11: SDRAM Clock Group Clocks
Name
ddr_dqs_clk
(8) The maximum frequency depends on the speed grade of the device.
Altera Corporation
Output Counter
C0
ddr_dqs_base_
clk
C1
ddr_2x_dqs_
base_clk
C2
ddr_dq_base_
clk
C5
h2f_user2_
base_clk
ddr_dqs_base_clk
SDRAM
C0
PLL
ddr_2x_dqs_base_clk
C1
ddr_dq_base_clk
C2
Unused
C3
C4 Unused
h2f_user2_base_clk
C5
SDRAM PLL C0
Clock Name Frequency
Varies
(8)
ddr_dqs_base_
clk x 2
ddr_dqs_base_
clk
osc1_clk
varies (8)
Frequency
Phase Shift Control
Yes
Yes
Yes
to Yes
Clock Gate ddr_dqs_clk
Clock Gate
ddr_2x_dqs_clk
Clock Gate
ddr_dq_clk
h2f_user2_clock
Clock Gate
Constraints and Notes
Clock for MPFE, single-port
controller, CSR access, and PHY
cv_5v4
2016.10.28
Clock Manager
Send Feedback