Altera cyclone V Technical Reference page 427

cv_5v4
2016.10.28
Module Instance
sysmgr
Offset:
0x704
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
I2C0USEFPGA Fields
Bit
0
sel
RGMII0USEFPGA
Selection between HPS Pins and FPGA Interface for RGMII0 signals. Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x714
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Manager
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0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select connection for I2C0. 0 : I2C0 uses HPS Pins. 1 :
I2C0 uses the FPGA Inteface.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
RGMII0USEFPGA
Register Address
0xFFD08704
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08714
5-233
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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