Altera cyclone V Technical Reference page 756

11-18
Interleaving Options
Figure 11-4: Non-interleaved Address Decoding
Bank Interleave Without Chip Select Interleave
Bank interleave without chip select interleave swaps row and bank from the non-interleaved address
mapping. This interleaving allows smaller data structures to spread across all banks in a chip.
Figure 11-5: Bank Interleave Without Chip Select Interleave Address Decoding
Bank Interleave with Chip Select Interleave
Bank interleave with chip select interleave moves the row address to the top, followed by chip select, then
bank, and finally column address. This interleaving allows smaller data structures to spread across multiple
banks and chips (giving access to 16 total banks for multithreaded access to blocks of memory). Memory
timing is degraded when switching between chips.
Figure 11-6: Bank Interleave With Chip Select Interleave Address Decoding
Altera Corporation
28 24
S B (2 :0 )
C =Column
28 24
S R ( 15 :0 )
28 24
R ( 15 :0 )
Address Decoding
(512 Mb x 16 DDR3 DRAM)
DDR 3 DDR 3
512 x 16 512 x 16
DDR 3 DDR 3
512 x 16 512 x 16
Controller
20 16 12
R ( 15 :0 )
Address Nomenclature
R =Row B =Bank
20 16 12
B ( 2 :0)
20 16 12
B ( 2 :0)
S
8 4
C ( 9 :0 )
S =Chip Select
8 4
C ( 9:0 )
8 4
C ( 9:0 )
SDRAM Controller Subsystem
cv_5v4
2016.10.28
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