Altera cyclone V Technical Reference page 234

Hard processor system
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5-40
hioctrl
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
hioctrl Fields
Bit
8
oct_cfgen_calstart
7
regrst
6
octrst
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
Name
Controls OCT calibration and OCT IO configuration
enable.
Value
0x0
0x1
Controls IO and DQS reset.
Value
0x0
0x1
Controls OCT reset.
Value
0x0
0x1
Bit Fields
25
24
23
22
Reserved
9
8
7
6
oct_
regrs
octrs
cfgen
t
t
_
RW
RW
calst
0x1
0x1
art
RW
0x0
Description
Description
Disables IO configuration (forced to a safe
value) in OCT calibration block.
Starts OCT calibration state machine and
enables IO configuration in OCT calibration
block.
Description
No reset.
Resets all IO registers and DQS registers.
Description
No reset.
Resets registers in the OCT.
21
20
19
18
5
4
3
2
dllrs
slew
wkpul
trist
t
lup
ate
RW
RW
0x0
RW
RW
0x1
0x0
0x0
cv_5v4
2016.10.28
17
16
1
0
busho
cfg
ld
RW 0x0
RW
0x0
Access
Reset
RW
0x0
RW
0x1
RW
0x1
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