Altera cyclone V Technical Reference page 986

14-40
Avoiding Glitches in the Card Clock Outputs
issued; no other commands (including a new RW_BLK) should be issued before the Data Transfer Over
status is set for the outstanding RW_BLK.
Before issuing a new data transfer command, the software should ensure that the card is not busy due to
any previous data transfer command. Before changing the card clock frequency, the software must ensure
that there are no data or command transfers in progress.
If the card is enumerated in SDR12 or SDR25 mode, the application must program the
bit[29] in the CMD register to 1'b1.
This programming should be done for all data transfer commands and non-data commands that are sent
to the card. When the
Hold Registers in the transmit path. The value of this bit should not be changed when a Command or Data
Transfer is in progress.
For more information on using the
card input hold time, refer to the latest version of the Synopsys DesignWare Cores Mobile Storage Host
Databook.
Avoiding Glitches in the Card Clock Outputs
To avoid glitches in the card clock outputs (
when changing the card clock frequency:
1. Before disabling the clocks, ensure that the card is not busy due to any previous data command. To
determine this, check for 0 in bit 9 of the STATUS register.
2. Update the Clock Enable register to disable all clocks. To ensure completion of any previous command
before this update, send a command to the CIU to update the clock registers by setting:
•
start_cmd
• "update clock registers only" bits
• "wait_previous data complete"
Note: Wait for the CIU to take the command by polling for 0 on the
3. Set the
to the CIU in order to update the clock registers; wait for the CIU to take the command.
4. Set
start_cmd
command to the CIU to update the clock registers; wait for the CIU to take the command.
Reading from a Card in Non-DMA Mode
When a card is read in non-DMA mode, the Data Transfer Over (RINTSTS[3]) interrupt occurs as soon
as the data transfer from the card is over. There still could be some data left in the FIFO, and the
RX_WMark interrupt may or may not occur, depending on the remaining bytes in the FIFO. Software
should read any remaining bytes upon seeing the Data Transfer Over (DTO) interrupt. While using the
external DMA interface for reading from a card, the DTO interrupt occurs only after all the data is flushed
to memory by the DMA Interface unit.
Writing to a Card in External DMA Mode
While writing to a card in external DMA mode, if an undefined-length transfer is selected by setting the
Byte Count register to 0, the DMA logic will likely request more data than it will send to the card, since it
has no way of knowing at which point the software will stop the transfer. The DMA request stops as soon
as the DTO is set by the CIU.
Altera Corporation
use_hold_reg
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†
bit
bit to update the Clock Divider and/or Clock Source registers, and send a command
start_cmd
to update the Clock Enable register in order to enable the required clocks and send a
†
†
†
†
†
bit is programmed to 1'b0, the SD/MMC controller bypasses the
and the implementation requirements for meeting the
use_hold_reg
†
sdmmc_cclk_out
†
†
†
†
†
†
), the software should use the following steps
†
start_cmd
cv_5v4
2016.10.28
use_hold_reg
†
†
bit.
†
†
SD/MMC Controller
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