Clock Manager; Features Of The Clock Manager - Altera cyclone V Technical Reference

2016.10.28
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The hard processor system (HPS) clock generation is centralized in the clock manager. The clock manager
is responsible for providing software-programmable clock control to configure all clocks generated in the
HPS. Clocks are organized in clock groups. A clock group is a set of clock signals that originate from the
same clock source. A phase-locked loop (PLL) clock group is a clock group where the clock source is a
common PLL voltage-controlled oscillator (VCO).

Features of the Clock Manager

The Clock Manager offers the following features:
• Generates and manages clocks in the HPS
• Contains the following PLL clock groups:
• PLL 0 (Main)—contains clocks for the Cortex-A9 microprocessor unit (MPU) subsystem, level 3
(L3) interconnect, level 4 (L4) peripheral bus, and debug
• PLL 1 (Peripheral)—contains clocks for PLL-driven peripherals
• SDRAM—contains clocks for the SDRAM subsystem
• Allows scaling of the MPU subsystem clocks without disabling peripheral and SDRAM clock groups
• Generates clock gate controls for enabling and disabling most clocks
• Initializes and sequences clocks for the following events:
• Cold reset
• Safe mode request from reset manager on warm reset
• Allows software to program clock characteristics, such as the following items discussed later in this
chapter:
• Input clock source for SDRAM and peripheral PLLs
• Multiplier range, divider range, and six post-scale counters for each PLL
• Output phases for SDRAM PLL outputs
• VCO enable for each PLL
• Bypass modes for each PLL
• Gate off individual clocks in all PLL clock groups
• Clear loss of lock status for each PLL
• Safe mode for Hardware-Managed clocks
• General-purpose I/O (GPIO) debounce clock divide
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