Altera cyclone V Technical Reference page 754

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ECC
Width Matching
The SDRAM controller automatically performs data width conversion.
ECC
The single-port controller supports memory ECC calculated by the controller.
The controller ECC employs standard Hamming logic to detect and correct single-bit errors and detect
double-bit errors. The controller ECC is available for 16-bit and 32-bit widths, each requiring an additional
8 bits of memory, resulting in an actual memory width of 24-bits and 40-bits, respectively.
Note: The level of ECC support is package dependent.
Functions the controller ECC provides are:
• Byte Writes
• ECC Write Backs
• Notification of ECC Errors
Byte Writes
The memory controller performs a read-modify-write operation to ensure that the ECC data remains valid
when a subset of the bits of a word is being written.
Byte writes with ECC enabled are executed as a read-modify-write. Typical operations only use a single
entry in the timer bank pool. Controller ECC enabled sub-word writes use two entries. The first operation
is a read and the second operation is a write. These two operations are transferred to the timer bank pool
with an address dependency so that the write cannot be performed until the read data has returned. This
approach ensures that any subsequent operations to the same address (from the same port) are executed
after the write operation, because they are ordered on the row list after the write operation.
If an entire word is being written (but less than a full burst) and the DM pins are connected, no read is
necessary and only that word is updated. If controller ECC is disabled, byte-writes have no performance
impact.
ECC Write Backs
If the controller ECC is enabled and a read operation results in a correctable ECC error, the controller
corrects the location in memory, if write backs are enabled. The correction results in scheduling a new
read-modify-write.
A new read is performed at the location to ensure that a write operation modifying the location is not
overwritten. The actual ECC correction operation is performed as a read-modify-write operation. ECC
write backs are enabled and disabled through the
register.
ctrlcfg
Note: Double-bit errors do not generate read-modify-write commands. Instead, double-bit error address
and count are reported through the
double-bit error interrupt can be enabled through the
Altera Corporation
Burst Length
16
cfg_enable_ecc_code_overwrites
and registers, respectively. In addition, a
erraddr dbecount
dramintr
SDRAM
LPDDR2
field in the
register.
SDRAM Controller Subsystem
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2016.10.28