Altera cyclone V Technical Reference page 802

11-64
portcfg
31 30
15 14
ctrlwidth Fields
Bit
1:0
ctrlwidth
portcfg
Each bit of the
memory accesses, the corresponding
then its
autopchen
Module Instance
sdr
Offset:
0x507C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
Name
This field specifies the SDRAM controller interface
width:
Value
0x0
0x1
0x2
Additionally, you must program the
register.
field maps to one of the control ports. If a port executes mostly sequential
autopchen
bit should be set to 1.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
8-bit interface width
16-bit (no ECC) or 24-bit (ECC enabled)
interface width
32-bit (no ECC) or 40-bit (ECC enabled)
interface width
bit should be 0. If the port has highly random accesses,
autopchen
Base Address
0xFFC20000
21 20 19 18
5 4 3 2
Access
dramifwidth
Register Address
0xFFC2507C
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
1 0
ctrlwidth
RW 0x0
Reset
RW 0x0
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