Altera cyclone V Technical Reference page 466

7-18
Interconnect Slave Properties
Slave
SP timer 0/1 32
2
I C 0/1/2/3
UART 0/1
CAN 0/1
GPIO 0/1/2
ACP ID
mapper CSR
FPGA
manager
CSR
DAP CSR
Quad SPI
flash CSR
SD/MMC
CSR
EMAC 0/1
CSR
System
manager
OSC1 timer
0/1
Watchdog 0/
1
Clock
manager
Reset
manager
Acceptance is based on the number of read, write, and total transactions.
(17)
The FIFO buffer depth for AXI is based on the AW, AR, R, W, and B channels. For AHB and APB, the depth
(18)
is based on W, A, and D channels.
Altera Corporation
I/F Width Clock
l4_sp_clk
32
l4_sp_clk
32
l4_sp_clk
32
l4_sp_clk
32
l4_mp_clk
32
l4_mp_clk
32
l4_mp_clk
32
l4_mp_clk
32
l4_mp_clk
32
l4_mp_clk
32
l4_mp_clk
32
osc1_clk
32
osc1_clk
32
osc1_clk
32
osc1_clk
32
osc1_clk
Mastered By
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 SP bus master
L4 MP bus master
L4 OSC1 bus master
L4 OSC1 bus master
L4 OSC1 bus master
L4 OSC1 bus master
L4 OSC1 bus master
Acceptance Buffer
(17)
Depth
(18)
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
1, 1, 1 2, 2, 2
System Interconnect
Send Feedback
cv_5v4
2016.10.28
Type
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB