Emac Hps Interface Initialization - Altera cyclone V Technical Reference

17-66

EMAC HPS Interface Initialization

be required. Routing the Ethernet signals through the FPGA is useful for designs that are pin-
limited in the HPS.
EMAC HPS Interface Initialization
To initialize the Ethernet controller to use the HPS interface, specific software steps must be followed
including selecting the correct PHY interface through the System Manager.
In general, the Ethernet Controller must be in a reset state during static configuration and the clock must
be active and valid before the Ethernet Controller is brought out of reset.
1. After the HPS is released from cold or warm reset, reset the Ethernet Controller module by setting the
appropriate
2. Configure the EMAC Controller clock to 250 MHz by programming the appropriate
emac*clk
3. Bring the Ethernet PHY out of reset to verify that there are RX PHY clocks.
4. When all the clocks are valid, program the following clock settings:
a. Set the
the RGMII PHY interface.
b. Disable the Ethernet Controller FPGA interfaces by clearing the
the System Manager (FPGA Interface group).
5. Configure all of the EMAC static settings if the user requires a different setting from the default value.
These settings include AXI AxCache signal values, which are programmed in
EMAC group of the System Manager.
6. Execute a register read back to confirm the clock and static configuration settings are valid.
7. After confirming the settings are valid, software can clear the
Reset Manager to bring the EMAC out of reset..
When these steps are completed, general Ethernet controller and DMA software initialization and
configuration can continue.
DMA Initialization
This section provides the instructions for initializing the DMA registers in the proper sequence. This
initialization sequence can be done after the EMAC interface initialization has been completed. Perform
the following steps to initialize the DMA:
1. Provide a software reset to reset all of the EMAC internal registers and logic. (DMA Register 0 (Bus
Mode Register) – bit 0).
2. Wait for the completion of the reset process (poll bit 0 of the DMA Register 0 (Bus Mode Register),
which is only cleared after the reset operation is completed).
3. Poll the bits of Register 11 (AXI Status) to confirm that all previously initiated (before software reset) or
ongoing transactions are complete.
Note: If the application cannot poll the register after soft reset (because of performance reasons), then
it is recommended that you continue with the next steps and check this register again (as
mentioned in step
4. Program the following fields to initialize the Bus Mode Register by setting values in DMA Register 0
(Bus Mode Register):
Altera Corporation
bit in the
emac permodrst
register in the Clock Manager.
field in the
physel_* ctrl
†
12
on page 1-67) before triggering the DMA operations.
†
register in the Reset Manager.
register of the System Manager (EMAC Group) to 0x1 to select
emac
†
value in the
cnt
bit in the
emac_* module
l3 register
bit in the register of the
permodrst
†
Ethernet Media Access Controller
Send Feedback
cv_5v4
2016.10.28
register of
in the