Main Connectivity Matrix - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Internally, the L3 interconnect is partitioned into the following subswitches:
• L3 interconnect
• Interconnect used to transfer high-throughput 64-bit data
• Operates at up to half the MPU main clock frequency
• Provides masters with low-latency connectivity to AXI bridges, on-chip memories, SDRAM, and
FPGA manager
• L3 master peripheral switch
• Used to connect memory-mastering peripherals to the interconnect
• 32-bit data width
• Operates at up to half the interconnect clock frequency
• L3 slave peripheral switch
• Used to provide access to level 3 and 4 slave interfaces for masters of the master peripheral and
interconnects
• 32-bit data width
• Five independent L4 buses
The L3 master and slave peripheral switches are fully-connected crossbars. The L3 interconnect is a
partially-connected crossbar. The following table shows the connectivity matrix of all the master and slave
interfaces of the L3 interconnect.

Main Connectivity Matrix

The L3 master and slave peripheral switches are fully-connected crossbars. The L3 interconnect is a
partially-connected crossbar. The following table shows the connectivity matrix of all the master and slave
interfaces of the L3 interconnect.
For details of the masters and slaves connected to the L3 master peripheral switch and L3 master peripheral
(13)
switch, refer to "Interconnect Block Diagram".
System Interconnect
Send Feedback
Main Connectivity Matrix
Altera Corporation
7-3