Altera cyclone V Technical Reference page 207
Hard processor system
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Also See for cyclone V:
- Device handbook (1077 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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cv_5v4
2016.10.28
USB Controller Group
Register
l3master
on page 5-
71
ECC Management Register Group
Register
l2
on page 5-74
ocram
on page 5-75
usb0
on page 5-76
usb1
on page 5-77
emac0
on page 5-78
emac1
on page 5-80
dma
on page 5-82
can0
on page 5-83
can1
on page 5-84
nand
on page 5-85
qspi
on page 5-87
sdmmc
on page 5-88
Pin Mux Control Group
Register
EMACIO0
on page 5-107
EMACIO1
on page 5-108
EMACIO2
on page 5-109
System Manager
Send Feedback
Offset
Width Acces
s
0x118
32
RW
Offset
Width Acces
s
0x140
32
RW
0x144
32
RW
0x148
32
RW
0x14C
32
RW
0x150
32
RW
0x154
32
RW
0x158
32
RW
0x15C
32
RW
0x160
32
RW
0x164
32
RW
0x168
32
RW
0x16C
32
RW
Offset
Width Acces
s
0x400
32
RW
0x404
32
RW
0x408
32
RW
System Manager Module Address Map
Reset Value
USB L3 Master HPROT Register
0xF
Reset Value
L2 Data RAM ECC Enable
0x0
Register
On-chip RAM ECC Enable
0x0
Register
USB0 RAM ECC Enable Register
0x0
USB1 RAM ECC Enable Register
0x0
EMAC0 RAM ECC Enable
0x0
Register
EMAC1 RAM ECC Enable
0x0
Register
DMA RAM ECC Enable Register
0x0
CAN0 RAM ECC Enable Register
0x0
CAN1 RAM ECC Enable Register
0x0
NAND RAM ECC Enable
0x0
Register
QSPI RAM ECC Enable Register
0x0
SDMMC RAM ECC Enable
0x0
Register
Reset Value
emac0_tx_clk Mux Selection
0x0
Register
emac0_tx_d0 Mux Selection
0x0
Register
emac0_tx_d1 Mux Selection
0x0
Register
5-13
Description
Description
Description
Altera Corporation
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