Altera cyclone V Technical Reference page 133

3-22
ctrl
Bit
12
scanmgrhsen
10
fpgamgrhsack
9
fpgamgrhsreq
8
fpgamgrhsen
6
sdrselfreqack
5
sdrselfrefreq
Altera Corporation
Name
Enables a handshake between the Reset Manager and
Scan Manager before a warm reset. The handshake is
used to warn the Scan Manager that a warm reset it
coming so it can prepare for it. When the Scan
Manager receives a warm reset handshake, the Scan
Manager drives its output clocks to a quiescent state
to avoid glitches. If set to 1, the Reset Manager makes
a request to the Scan Managerbefore asserting warm
reset signals. However if the Scan Manager is already
in warm reset, the handshake is skipped. If set to 0,
the handshake is skipped.
This is the acknowlege (high active) that the FPGA
manager has successfully idled its output clock.
Software writes this field 1 to request to the FPGA
Manager to idle its output clock. Software waits for
the FPGAMGRHSACK to be 1 and then writes this
field to 0. Note that it is possible for the FPGA
Manager to never assert FPGAMGRHSACK so
software should timeout in this case.
Enables a handshake between the Reset Manager and
FPGA Manager before a warm reset. The handshake
is used to warn the FPGA Manager that a warm reset
it coming so it can prepare for it. When the FPGA
Manager receives a warm reset handshake, the FPGA
Manager drives its output clock to a quiescent state to
avoid glitches. If set to 1, the Manager makes a
request to the FPGA Managerbefore asserting warm
reset signals. However if the FPGA Manager is
already in warm reset, the handshake is skipped. If set
to 0, the handshake is skipped.
This is the acknowlege for a SDRAM self-refresh
mode request initiated by the SDRSELFREFREQ
field. A 1 indicates that the SDRAM Controller
Subsystem has put the SDRAM devices into self-
refresh mode.
Software writes this field 1 to request to the SDRAM
Controller Subsystem that it puts the SDRAM devices
into self-refresh mode. This is done to preserve
SDRAM contents across a software warm reset.
Software waits for the SDRSELFREFACK to be 1 and
then writes this field to 0. Note that it is possible for
the SDRAM Controller Subsystem to never assert
SDRSELFREFACK so software should timeout if
SDRSELFREFACK is never asserted.
Description
cv_5v4
2016.10.28
Access Reset
RW 0x0
RO 0x0
RW 0x0
RW 0x0
RO 0x0
RW 0x0
Reset Manager
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