Altera cyclone V Technical Reference page 88

cv_5v4
2016.10.28
Bit
21:16
denom
15:3
numer
2
pwrdn
1
en
0
bgpwrdn
misc
Contains VCO control signals and other PLL control signals need to be controllable through register.
Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x84
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved saten faste
RW
0x1
0x0
Clock Manager
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Name
Denominator in VCO output frequency equation. For
incremental frequency change, if the new value lead
to less than 20% of the frequency change, this value
can be changed without resetting the PLL. The
Numerator and Denominator can not be changed at
the same time for incremental frequency changed.
Numerator in VCO output frequency equation. For
incremental frequency change, if the new value lead
to less than 20% of the frequency change, this value
can be changed without resetting the PLL. The
Numerator and Denominator can not be changed at
the same time for incremental frequency changed.
If '1', power down analog circuitry. If '0', analog
circuitry not powered down.
If '1', VCO is enabled. If '0', VCO is in reset.
If '1', powers down bandgap. If '0', bandgap is not
power down.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
n
RW
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
bwadj
RW 0x1
Access
Register Address
0xFFD04084
21 20 19 18
5 4 3 2
2-51
misc
Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x0
RW 0x1
17 16
1 0
bwadjen
RW 0x0
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