Altera cyclone V Technical Reference page 575

cv_5v4
2016.10.28
fn_mod Fields
Bit
1
wr
0
rd
NAND Register Descriptions
Registers associated with the NAND slave interface. This slave is used by the DMA controller built into the
NAND flash controller to access slaves attached to the L3/L4 Interconnect.
Offset:
0x9000
read_qos on page 7-127
QoS (Quality of Service) value for the read channel.
write_qos
QoS (Quality of Service) value for the write channel.
fn_mod on page 7-129
Sets the block issuing capability to multiple or single outstanding transactions.
read_qos
QoS (Quality of Service) value for the read channel.
Module Instance
l3regs
Offset:
0x4B100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
System Interconnect
Send Feedback
Name
Value
0x0
0x1
Value
0x0
0x1
on page 7-128
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Multiple outstanding write transactions
Only a single outstanding write transaction
Description
Multiple outstanding read transactions
Only a single outstanding read transaction
Base Address
NAND Register Descriptions
Access
Register Address
0xFF84B100
7-127
Reset
RW 0x0
RW 0x0
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