Programming Guidelines For Energy Efficient Ethernet - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
1. Disable the transmit DMA (if applicable), by clearing bit 13 (Start or Stop Transmission Command) of
Register 6 (Operation Mode Register). †
2. Wait for any previous frame transmissions to complete. You can check this by reading the appropriate
bits of Register 9 (Debug Register). †
3. Disable the EMAC transmitter and EMAC receiver by clearing Bit 3 (TE) and Bit 2 (RE) in Register 0
(MAC Configuration Register). †
4. Disable the receive DMA (if applicable), after making sure that the data in the RX FIFO buffer is
transferred to the system memory (by reading Register 9 (Debug Register). †
5. Make sure that both the TX FIFO buffer and RX FIFO buffer are empty. †
6. To re-start the operation, first start the DMA and then enable the EMAC transmitter and receiver. †

Programming Guidelines for Energy Efficient Ethernet

Entering and Exiting the TX LPI Mode
The Energy Efficient Ethernet (EEE) feature is available in the EMAC. To use it, perform the following
steps during EMAC initialization:
1. Read the PHY register through the MDIO interface, check if the remote end has the EEE capability,
and then negotiate the timer values.
2. Program the PHY registers through the MDIO interface (including the RX_CLK_stoppable bit that
indicates to the PHY whether to stop the RX clock in LPI mode.)
3. Program Bits[16:5], LST, and Bits[15:0], TWT, in Register 13 (LPI Timers Control Register).
4. Read the link status of the PHY chip by using the MDIO interface and update Bit 17 (PLS) of Register
12 (LPI Control and Status Register) accordingly. This update should be done whenever the link status
in the PHY changes.
5. Set Bit 16 (LPIEN) of Register 12 (LPI Control and Status Register) to make the MAC enter the LPI
state. The MAC enters the LPI mode after completing the transmission in progress and sets Bit 0
(TLPIEN).
Note: To make the MAC enter the LPI state only after it completes the transmission of all queued
frames in the TX FIFO buffer, you should set Bit 19 (LPITXA) in Register 12 (LPI Control and
Status Register).
Note: To switch off the transmit clock during the LPI state, use the
signal for gating the clock input.
Note: To switch off the CSR clock or power to the rest of the system during the LPI state, you should
wait for the TLPIEN interrupt of Register 12 (LPI Control and Status Register) to be generated.
Restore the clocks before performing step
LPI state.
6. Clear Bit 16 (LPIEN) of Register 12 (LPI Control and Status Register) to bring the MAC out of the LPI
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state.
The MAC waits for the time programmed in Bits [15:0], TWT, before setting the TLPIEX interrupt status
bit and resuming the transmission.
Gating Off the CSR Clock in the LPI Mode
You can gate off the CSR clock to save the power when the MAC is in the Low-Power Idle (LPI) mode.
Gating Off the CSR Clock in the RX LPI Mode
The following operations are performed when the MAC receives the LPI pattern from the PHY. †
Ethernet Media Access Controller
Send Feedback
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Programming Guidelines for Energy Efficient Ethernet
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on page 1-69 when you want to come out of the
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sbd_tx_clk_gating_ctrl_o
Altera Corporation
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